AMD is hiring for the role of Sr. Verification Design Engineer for Bachelor/Master’s degree in Electrical/Electronics/Computer Engineering & Master preferred in Hyderabad, Telangana, India. Candidate should have a minimum of 6+ years of SOC design and verification experience. Interested candidates can apply for this recruitment drive and register through the given link. The detailed eligibility criteria to qualify and the application process are given below.
Job Summary of AMD:
Company Name: AMD
Job Profile: Sr. Verification Design Engineer
Qualification: Bachelor/Master’s degree in Electrical/Electronics/Computer Engineering & Master preferred
Experience: Minimum 6+ years of SOC design and verification experience
Location: Hyderabad
Employment Type: Full-Time
Job Function: Engineering, Information Technology
Role
This person will be part of the next-generation Server SoC Verification team. Requires strong hands-on knowledge of all facets of the IC design process and a good understanding of Verilog/SV/UVM
Key Responsibilities
- Work with the global Front-End design team for verification of large scale ASIC microprocessor, network-on-chip, security, and SOC clock and reset functions.
- Develop and implement System Verilog UVM constrained random test sequences and C-based directed tests.
- Improve existing UVM test bench with advanced design verification methodology.
- Work on power-aware flow and bring up NLP for Power Gating simulation.
- Develop and execute verification test plans and testbench component plans and drive reviews with peers and stakeholders.
- Develop testbench components including stimulus drivers, monitors and checkers.
- Develop, simulate and debug directed and random stimulus and assembly level tests.
- Develop and analyze assertions and coverage terms. Participate in technical reviews of the specifications, design and test plans. Identify and address areas of concern to meet design quality objectives.
- Develop tools, infrastructure, processes and flows to enable functional verification.
- Maintain and improve existing functional verification infrastructure and methodology.
- Independently develop quality, timely and cost-effective solutions.
Preferred Experience
- You should have minimum 6+ years of SOC design and verification experience
- You should have excellent at scripts, C++/UVM OOP languages
- You should have experience in Verilog and System Verilog languages
- You should have a strong understanding of computer architecture and ASIC design flow
- You should have experience with bus protocols (AXI, AHB, other)
- Build C/C++/UVM model for simulation
- Build a test bench and monitors for DUT
- Compose test plan and validation vectors to ensure functional completeness
- Debug function/performance bugs of graphics, APU and server chips
- Prefer 5 or more years of experience in the ASIC design and verification industry
- Familiar with Linux Environment (including shell scripting and Linux GNU tools)
- You should have experience with design for verification (assertion-based design strategies, code coverage, functional coverage, test plan, gate-level simulation, back-annotation etc.)
- Should be versatile in any one of the high-level verification flows such as SV, UVM, C++, etc., as well as knowledge of industry-standard tools for verification
- You should have excellent communication skills (both written and oral)
- You should have strong problem-solving skills
Academic Credentials
- Candidate must possess a Bachelor/Master’s degree in Electrical/Electronics/Computer Engineering. Master preferred
How to Apply AMD for the role of Sr. Verification Design Engineer?
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